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LA72715NV
No.A1770-10/13
Fig.1 DATA STRUCTURE “WRITE” mode
START Condition
Slave Address
R/W
L
ACK
Control data
ACK
STOP condition
Fig.2 DATA STRUCTURE “READ” mode
START condition
Slave Address
R/W
H
ACK
Internal Data *
ACK
STOP condition
The output data synchronizes with the clock of SCL pin. Then the ACK output is made after the output data.
bit8 is result of STERO DET
(H : STEREO)
bit7 is result of BILINGUAL DET (H : BILINGUAL)
bit6 is Initial Condition ‘H’
bit5 to bit1 are fixed to ‘L’
(3) Initialize
This IC is initialized for circuit protection. Initial condition is “01h (Main-mode) ”.
Reference
Parameter
Symbol
min
max
unit
LOW level input voltage
VIL
-0.5
1.5
V
HIGH level input voltage
VIH
2.5
5.5
V
LOW level output current
IOL
3.0
mA
SCL clock frequency
fSCL
0
100
kHz
Set-up time for a repeated START condition
tSU : STA
4.7
μs
Hold time START condition. After this period, the first clock pulse is generated
tHD : STA
4.0
μs
LOW period of the SCL clock
tLOW
4.7
μs
Rise time of both SDA and SDL signals
tR
0
1.0
μs
HIGH period of the SCL clock
tHIGH
4.0
μs
Fall time of both SDA and SDL signals
tF
0
1.0
μs
Data hold time
tHD : DAT
0
μs
Data set-up time
tSU : DAT
250
ns
Set-up time for STOP condition
tSU : STO
4.0
μs
BUS free time between a STOP and START condition
tBUF
4.7
μs
Definition of Timing
t HD:STA
t SU:STA
t LOW
t R
t F
t HIGH
t HD:DATA
t SU:DAT
t SU:STO
t BUF
SCL
SDA
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